High voltage semiconductor device utilizing a deep trench structure

ABSTRACT

A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

BACKGROUND

The present disclosure relates generally to semiconductor devices and,more specifically, to a high voltage semiconductor device utilizing adeep trench isolation structure.

As field effect transistors (FET's) such as metal-oxide-semiconductor(MOS) devices are adopted for higher and higher power or voltageapplications, problems arise with respect to the current vs. voltageresponse of the device.

In MOS devices, such as high voltage lateral diffused metal-oxidesemiconductor (HVLDMOS) structures, the gate electrode typically mayoverlap the non-active region due to processing and design issues. Whena high enough voltage is applied to the gate, a channel in thenon-active region may open up, allowing a leakage current to flowthrough it, which causes the device's current vs.voltage response todeviate from the desired linear relationship.

Accordingly, it would be desirable to provide an improved high voltagesemiconductor device and method of manufacture thereof absent thedisadvantages discussed above.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a top view illustrating an embodiment of a high voltagesemiconductor device constructed according to aspects of the presentdisclosure.

FIG. 2 is a cross-sectional view of the embodiment of the high voltagesemiconductor device of FIG. 1 taken along section line 2-2.

FIG. 3 is a cross-sectional view of the embodiment of the high voltagesemiconductor device of FIG. 1 taken along section line 3-3.

FIG. 4 is a top view illustrating another embodiment of a high voltagesemiconductor device constructed according to aspects of the presentdisclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof various embodiments. Specific examples of components and arrangementsare described below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

In one embodiment, a high voltage semiconductor device 100, FIG. 1,includes a substrate 102. Substrate 102 may include an elementarysemiconductor (such as crystal silicon, polycrystalline silicon,amorphous silicon and germanium), a compound semiconductor (such assilicon carbide and gallium arsenide), an alloy semiconductor (such assilicon germanium, gallium arsenide phosphide, aluminum indium arsenide,aluminum gallium arsenide and gallium indium phosphide), combinationsthereof and/or other materials. Substrate 102 may also include asemiconductor material on an insulator, such as a silicon-on-insulator(SOI) substrate, a silicon on sapphire (SOS) substrate, or a thin filmtransistor (TFT). In one embodiment, substrate 102 may also include adoped epitaxial layer. Substrate 102 may also include a multiple siliconstructure or a multilayer, compound semiconductor structure.

Located on substrate 102 are a P-well region 104 and a N-well region106. P-well region 104 and N-well region 106 may be part of substrate102, and formed by implantation. Alternatively, P-well region 104 andN-well region 106 may be an epi layer such as a Si epi layer formed byepi processing. P-well region 104 has a p-dopant such as Boron, andN-well region 106 has an n-dopant such as phosphorus. In one embodiment,well regions 104 and 106 can be formed by growing a sacrificial oxide onsubstrate 102, opening a pattern for the location of the N-well orP-well, and using a chained-implantation procedure, as is known in theart.

There might be an insulator layer (not shown) between substrate 102 andoverlying P-well 104 and N-well regions 106. In one embodiment, theinsulator layer may be a buried oxide (BOX) layer, such as that formedby separation by implantation of oxygen (SIMOX) technology, or waferbonding. The insulator layer may also be formed over the substrate 102by thermal oxidation, atomic layer deposition (ALD), chemical vapordeposition (CVD), physical vapor deposition (PVD) and/or otherprocesses. Chemical mechanical polishing (CMP) and/or other methods maybe employed to attain a desired thickness of the insulator layer.Moreover, although not limited by the scope of the present disclosure,the insulator layer may include oxide, silicon oxide, silicon nitride,silicon oxynitride, hafnium oxide, zirconium oxide, aluminum oxide, ahafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, combinations thereof and/orother materials.

P-well region 104 includes on its surface a source region 108 and a bodycontact feature 110 adjacent the source region 108. Source region 108includes source ends 112 and 114 located opposite each other. Bodycontact feature 110 includes body contact ends 116 and 118 locatedopposite each other. N-well region 106 includes on its surface a drainregion 120. Drain region 120 includes drain ends 122 and 124 locatedopposite each other. In one embodiment, source region 108 and drainregion 120 are source/drain regions of a metal-oxide-semiconductorfield-effect-transistor (MOSFET) or other type of transistor such aslateral diffused MOS (LDMOS), or vertical diffused MOS (VDMOS).Accordingly, source region 108 and drain region 120 may be doped with ap-type impurity (such as boron) and/or an n-type impurity (such asphosphorous). The source and drain for a MOSFET may be formed by ionimplantation and/or diffusion. A rapid thermal annealing (RTA) step maybe used to activate the implanted dopants. The source and drain may havedifferent doping profiles formed by multi-step implantation. Also, thesource and drain may have different structures, such as raised,recessed, or strained. Body contact feature 110 may function as a guardring in a high power MOS device. Body contact feature 110 may be p-typedoped with higher concentration of p-type impurity (such as boron) toprovide a contact for connecting P-well region 104.

Source region 108, body contact feature 110, and drain region 120 areeach substantially of width W₁, and located on device 100 such thatsource end 114, body contact end 118, and drain end 124 all lie along aline 126, and source end 112, body contact end 116, and drain end 122all lie along a line 128. Source region 108, body contact feature 110,and drain region 120 occupy a region between lines 126 and 128, with theregion outside of lines 126 and 128 defined as a non-active region.

A gate electrode 130 is located above P-well region 104 and N-wellregion 106. Gate electrode is of width W_(g), and exists in the regionbetween lines 126 and 128 while also extending out into the non-activeregion beyond lines 126 and 128. Gate electrode 130 may be formed bymany methods, including but not limited to CVD, PVD, silicidation,plating, and ALD. The gate electrode may have multi-layer structure,such as doped polysilicon layer, and/or a layer of metal such as Ti, Ta,TiN, TaN, NiSi, and CoSi. The gate electrode may include more processingduring formation such as implant doping for polysilicon, or annealingfor silicidation.

Referring to FIG. 2, which is a cross sectional view of the embodimentof FIG. 1 taken along dotted line 132, device 100 includes an isolationfeature 136 and 138 located in N-well region 106. Isolation feature 138has length S. An isolation feature 140 is also located in P-well region104. Isolation features 136, 138, and 140 may utilize isolationtechnology such as local oxidation of silicon (LOCOS) and shallow trenchisolation (STI). In one embodiment, the depth of isolation features 136,138, and 140 is less than approximately 0.5 μm as measured verticallyfrom a surface 160, depending on the device technology. LOCOS mayinclude thermal oxidation using a patterned mask layer. STI may includedry etching a trench in a substrate and filling the trench by insulatormaterials such as silicon oxide, silicon nitride, or silicon oxynitride.The trench may have a multi-layer structure such as a thermal oxideliner layer with silicon nitride filling the trench. In one embodiment,the STI structure may be created using a process sequence such as:growing a pad oxide, forming a low pressure chemical vapor deposition(LPCVD) nitride layer, patterning an STI opening using photoresist andmasking, etching a trench in the substrate, optionally growing a thermaloxide trench liner to improve the trench interface, filling the trenchwith CVD oxide, using chemical mechanical planarization (CMP) to etchback, and using nitride stripping to leave the STI structure.

Semiconductor device 100 includes a pair of spacers 142 and 144 adjacentto gate electrode 130 as shown. Spacers 142 and 144 are positioned onboth sides of the gate electrode 130, and may include a dielectricmaterial such as silicon nitride, silicon oxide, silicon carbide,silicon oxynitride, or combinations thereof. Spacers 142 and 144 may beformed by depositing dielectric material and then dry-etching.

Semiconductor device 100 further includes a gate dielectric 146 adjacentto gate electrode 130. The gate electrode 130 may extend from a sourceedge 148 of source region 108 to a region above isolation feature 138 asshown. In one embodiment, gate dielectric 146 may extend from sourceedge 148 of source region 108 to an isolation edge 150 of isolationfeature 138. The gate length L is defined as the portion of gateelectrode 130 which exists over P-well region 104. Gate dielectricmaterials may include silicon oxide, silicon oxynitride, or a high kdielectric, such as hafnium oxide, hafnium silicide, hafrium siliconoxide, hafnium silicon oxynitride, zirconium oxide, aluminum oxide, ahafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, silicon nitride, Tantalumpentoxide or combinations thereof. Gate dielectric 146 may be formed bythermal oxide, ALD, CVD, or PVD. The gate dielectric may havemulti-layer structure, such as first layer of Silicon oxide by thermaloxidation, and a second layer of high K material. The gate dielectric146 may include more processing during formation such as nitrogentreatment of thermal oxide layer, and/or annealing of the gatedielectric stack including both silicon oxide and a high K layer.

Semiconductor device features including drain region 120, source region108, body contact feature 110, and gate electrode 130 may be connectedto an overlying interconnects structure (not shown) through lowresistant interfaces such as metal silicide including silicide, cobaltsilicide, tungsten silicide, titanium silicide, and tantalum silicide.

Referring back to FIG. 1, semiconductor device 100 includes a deeptrench structure 152 and 154. Deep trench structure 152 is locatedparallel to line 126, and a distance W₂ from it and source end 114, bodycontact end 118, and drain end 124. Deep trench structure 154 is locatedparallel to line 128, and a distance W₃ from it and source end 112, bodycontact end 116, and drain end 122.

FIG. 3 is a cross sectional view of the embodiment of FIG. 1 taken alongthe dotted line 156, and shows the deep trench structure 152 whichextends to a depth greater than that of isolation features 136, 138 and140 in FIG. 2. The depth of the deep trench isolation (DTI) structure154 may vary from approximately 0.5 μm to approximately 5 μm, asmeasured vertically from a top surface 160, depending on the devicetechnology. The depth of DTI structure 154 (cross section not shown) mayalso vary from approximately 0.5 μm to approximately 5 μm, as measuredvertically from the top surface 158, depending on the device technology.The DTI structures typically have a thickness more than approximately 1μm.

The DTI structure may be created using a process sequence such as:forming a high aspect ratio trench by patterning an opening usingphotoresist and masking, etching a trench in the semiconductor substrateby dry etching, wet etching, or a multi-step combination thereof,optionally forming at least one layer of trench liner to improve atrench interface, filling the trench with dielectric material such assilicon oxide by CVD, and using CMP or etch-back to remove the excess ofdielectric material above the substrate. In another embodiment, filledmaterials can be a plurality of dielectric materials having amultiple-layer structure. One of those filled materials can even be aair, resulting in an air gap as part of the deep trench structure. Inanother embodiment, a part of the trench may be filled by semiconductormaterial which is isolated by dielectric liner layer(s). Thesemiconductor layer may be silicon formed by epi growth from siliconsubstrate in the bottom of the trench opening.

In one embodiment, gate length L is about 3 μm and the length S ofisolation feature 138 is approximately 3 μm. W₂ and W₃ may be chosen asapproximately 0.5 μm. In this configuration, the non-ideal channelexisting in the non-active region outside of lines 126 and 128 iselectrically cut off by the DTI structure. Only the portion of thenon-ideal channel, which exists from line 126 and 128 to the closestedge of their respective deep trench structures 152 and 154, will allowa leakage current to flow through it when a high voltage is applied tothe gate. Since W₂+W₃, the non-ideal channel, is small relative to W₁,the ideal channel, relatively very little leakage current exists, andhence non-linear current-vs.-voltage responses in the device aresubstantially eliminated.

The DTI structures may have a different cross-sectional profiles,including such a profile with straight, tilted, or curved sidewalls,depending on the device technology. A curved sidewall profile may have alarger diameter or a smaller diameter at the top opening of the trenchas compared with that of the bottom opening of the trench.

The DTI structures may have different patterns according to design andfabrication considerations. In one embodiment, the DTI structures havetwo-straight-line patterns such as the deep trench structures 152 and154, as shown in FIG. 1. In another embodiment, the DTI structures maybe angled trenches, broken or non-continuous trenches, or trenches in aclosed pattern. A closed deep trench structure 158, like the one shownin FIG. 4, may partially underlay a plurality of portions of gateelectrode 130 extended beyond the edge of lines 126 and 128, andencircle the device. Such an embodiment will additionally allowsemiconductor device 100 to be isolated from neighboring devices (notshown) when the high voltages applied to it might cause currents amongneighboring devices otherwise.

Further embodiments may also provide a transistor device. Transistordevices include, but are not limited to, LDMOS, VDMOS, other types ofhigh power MOS transistors, fin structure fieled effect transistors(FinFET), and strained MOS structures.

The foregoing has outlined features of several embodiments. Thoseskilled in the art should appreciate that they may readily use thepresent disclosure as a basis for designing or modifying other processesand structures for carrying out the same purposes and/or achieving thesame advantages of the embodiments introduced herein. Those skilled inthe art should also realize that such equivalent constructions do notdepart from the spirit and scope of the present discloser, and that theymay make various changes, substitutions and alterations herein withoutdeparting from the spirit and scope of the present disclosure.

1. A semiconductor device comprising: a substrate including a source anddrain, the source having a first edge and the drain having a first edge;a gate between the source and drain, the gate having a first portion;and a first deep trench structure located under the first portion of thegate and proximate to the first edge of the source and the first edge ofthe drain.
 2. The semiconductor device of claim 1 further comprising:the source having a second edge and the drain having a second edge; thegate having a second portion; and a second deep trench structure locatedunder the second portion of the gate and proximate to the second edge ofthe source and the second edge of the drain.
 3. The semiconductor deviceof claim 2 wherein the first edge of the source and drain areapproximately parallel to the second edge of the source and drain, andwherein the first and second deep trench structures are approximatelyparallel the first and second edges, respectively.
 4. The semiconductordevice of claim 1 wherein the first deep trench structure has a depthgreater than 0.5 μm.
 5. The semiconductor device of claim 1 wherein thefirst deep trench structure exhibits a geometry selected from the groupconsisting of a straight line, an angled line, a broken line, and acombination thereof.
 6. The semiconductor device of claim 1 furthercomprising: an outside edge on the source; an outside edge on the drain;and the first deep trench structure having a length extending at leastfrom the outside edge of the source to the outside edge of the drain. 7.The semiconductor device of claim 1 wherein the first deep trenchstructure is substantially filled in with a material selected from thegroup consisting of silicon dioxide, silicon nitride, siliconoxynitride, a high k material, and a combination thereof.
 8. Thesemiconductor device of claim 1 wherein the substrate is made of amaterial selected from the group consisting of crystal silicon,polycrystalline silicon, amorphous silicon, germanium, diamond, silicongermanium, silicon carbide, gallium arsenic, indium phosphide,semiconductor on insulator, and a combination thereof.
 9. Thesemiconductor device of claim 1 wherein the device includes a strainedMOS structure.
 10. The semiconductor device of claim 1 furthercomprising: a neighboring semiconductor device; and a first shallowtrench isolation structure located between the semiconductor device andthe neighboring semiconductor device.
 11. The semiconductor device ofclaim 10 further comprising: a second shallow trench isolation structureadjacent to the drain wherein the drain is situated between the firstshallow trench isolation structure and the second shallow trenchisolation structure.
 12. The semiconductor device of claim 11 whereinthe gate is extended to partially overlay the second shallow trenchisolation structure.
 13. The semiconductor device of claim 1 furthercomprising: a body contact feature adjacent to the source.
 14. Thesemiconductor device of claim 1 wherein the gate includes a gateelectrode and a gate dielectric
 15. The semiconductor device of claim 15wherein the gate electrode is made of a material selected from the groupconsisting of doped polysilicon, metal, metal alloy, metal silicide, anda combination thereof.
 16. The semiconductor device of claim 15 whereinthe gate dielectric is made of a material selected from the groupconsisting of silicon oxide, silicon oxynitride, a high k material, anda combination thereof.
 17. The semiconductor device of claim 1 whereinthe first deep trench structure extends around the entire device.
 18. Asemiconductor device comprising: a substrate including a source and adrain, the source having a first edge and the drain having a first edge;a gate electrode on the substrate and between the source and drain, afirst portion of the gate electrode extending past the first edge of thesource and the first edge of the drain; a first deep trench structurelocated under the first portion of the gate electrode and proximate tothe first edge of the source and the first edge of the drain.
 19. Thesemiconductor device of claim 18 further comprising: the source having asecond edge and the drain having a second edge; a second portion of thegate electrode extending past the second edge of the source and thesecond edge of the drain; a second deep trench structure located underthe second portion of the gate electrode and proximate to the secondedge of the source and the second edge of the drain.
 20. Thesemiconductor device of claim 19 wherein the first edge of the source isapproximately parallel to the second edge of the source, the first edgeof the drain is approximately parallel to the second edge of the drain,the first deep trench structure is approximately parallel to the firstedges and the second deep trench structure is approximately parallel tothe second edges.
 21. The semiconductor device of claim 18 wherein thefirst deep trench structure has a depth greater than 0.5 μm.
 22. Thesemiconductor device of claim 18 wherein the first deep trench exhibitsa geometry selected from the group consisting of a straight line, anangled line, a broken line, and a combination thereof.
 23. Thesemiconductor device of claim 18 further comprising: an outside edge onthe source; an outside edge on the drain; and the first deep trenchhaving a length extending at least from the outside edge of the sourceto the outside edge of the drain.
 24. The semiconductor device of claim18 wherein the first deep trench structure is substantially filled inwith a material selected from the group consisting of silicon dioxide,silicon nitride, silicon oxynitride, a high k material, and acombination thereof.
 25. The semiconductor device of claim 18 whereinthe substrate is made of a material selected from the group consistingof crystal silicon, polycrystalline silicon, amorphous silicon,germanium, diamond, silicon germanium, silicon carbide, gallium arsenic,indium phosphide, semiconductor on insulator, and a combination thereof.26. The semiconductor device of claim 18 wherein the device includes astrained MOS structure.
 27. The semiconductor device of claim 18 furthercomprising: a neighboring semiconductor device; and a first shallowtrench isolation structure located between the semiconductor device andthe neighboring semiconductor device.
 28. The semiconductor device ofclaim 27 further comprising: a second shallow trench isolation structureadjacent to the drain wherein the drain is situated between the firstshallow trench isolation structure and the second shallow trenchisolation structure.
 29. The semiconductor device of claim 28 whereinthe gate is extended to partially overlay the second shallow trenchisolation structure.
 30. The semiconductor device of claim 18 furthercomprising: a body contact feature adjacent to the source.
 31. Thesemiconductor device of claim 18 further comprising: a gate dielectricadjacent to the gate electrode.
 32. The semiconductor device of claim 18wherein the gate electrode is made of a material selected from the groupconsisting of doped polysilicon, metal, metal alloy, metal silicide, anda combination thereof.
 33. The semiconductor device of claim 31 whereinthe gate dielectric is made of a material selected from the groupconsisting of silicon oxide, silicon oxynitride, a high k material, anda combination thereof.
 34. The semiconductor device of claim 18 whereinthe first deep trench structure extends around the entire device.
 35. Asemiconductor device comprising: a substrate having a source and adrain, the source and the drain having widths that are substantiallyequal and each having a first edge substantially located along a commonline on the substrate; a gate electrode on the substrate and between thesource and the drain, the gate electrode having a first portionextending past the first edge of the source and the first edge of thedrain; a first deep trench structure located under the first portion ofthe gate electrode, the first deep trench structure parallel to thecommon line on the substrate and proximate to the first edge of thesource and the first edge of the drain.
 36. The semiconductor device ofclaim 35 further comprising: the source and drain each having a secondedge parallel to their respective first edges; a second portion of thegate electrode extending past the second edges of the source and thedrain; a second deep trench structure located under the second portionof the gate electrode and proximate to the second edges of the sourceand the drain.
 37. The semiconductor device of claim 35 wherein thefirst deep trench structure is substantially deeper than 0.5 μm.
 38. Thesemiconductor device of claim 35 further comprising: an outside edge onthe source; an outside edge on the drain; and the first deep trenchstructure having a length extending at least from the outside edge ofthe source to the outside edge of the drain.
 39. The semiconductordevice of claim 35 wherein the first deep trench structure issubstantially filled in with a material selected from the groupconsisting of silicon dioxide, silicon nitride, silicon oxynitride, ahigh k material, and a combination thereof.
 40. The semiconductor deviceof claim 35 wherein the substrate is made of a material selected fromthe group consisting of crystal silicon, polycrystalline silicon,amorphous silicon, germanium, diamond, silicon germanium, siliconcarbide, gallium arsenic, indium phosphide, semiconductor on insulator,and a combination thereof.
 41. The semiconductor device of claim 35wherein the device includes a strained MOS structure.
 42. Thesemiconductor device of claim 35 further comprising: a neighboringsemiconductor device; and a first shallow trench isolation structurebetween the semiconductor device and the neighboring semiconductordevice.
 43. The semiconductor device of claim 42 further comprising: asecond shallow trench isolation structure adjacent to the drain whereinthe drain is situated between the first shallow trench isolationstructure and the second shallow trench isolation structure.
 44. Thesemiconductor device of claim 43 wherein the gate is extended topartially overlay the second shallow trench isolation structure.
 45. Thesemiconductor device of claim 35 further comprising: a body contactfeature adjacent to the source.
 46. The semiconductor device of claim 35further comprising: a gate dielectric adjacent to the gate electrode.47. The semiconductor device of claim 35 wherein the gate electrode ismade of a material selected from the group consisting of dopedpolysilicon, metal, metal alloy, metal silicide, and a combinationthereof.
 48. The semiconductor device of claim 46 wherein the gatedielectric is made of a material selected from the group consisting ofsilicon oxide, silicon oxynitride, a high k material, and a combinationthereof.
 49. The semiconductor device of claim 35 wherein the first deeptrench structure extends around the entire device.
 50. A semiconductordevice comprising: a substrate including a source and a drain, thesource having a first edge and the drain having a first edge; a gateelectrode on the substrate and between the source and drain, a firstportion of the gate electrode extending past the first edge of thesource and the first edge of the drain; a current channel located in aregion where the gate electrode extends beyond the first edge of thesource and the first edge of the drain, the current channel allowing aleakage current to flow in the device; a first deep trench structurelocated under the first portion of the gate electrode and proximate tothe first edge of the source and the first edge of the drain, wherebythe first deep trench structure is located close enough to the firstedge of the source and the first edge of the drain to substantiallyeliminate the leakage current flow through the current channel.
 51. Amethod of manufacturing a microelectronic device, comprising: forming asubstrate including a source and a drain; forming a gate between thesource and drain; and forming a deep trench structure under a portion ofthe gate and proximate to an edge of the source and drain.